1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a dual isolation structure and a method of fabricating the same.
2. Discussion of the Related Art
In the semiconductor arts, there continues to be an ever-increasing demand for a high level of power transmission, for high speed switching ability during power conversion, and for various applications of power IC products in power control systems. Power IC products are widely used in automotive electronic componentry as well as in hard disk drive (HDD) and in video tape recording (VTR) systems. Double-diffused MOS transistors (DMOS Tr) offer the combination of high-current processing ability and low on-resistance per surface area; therefore DMOS transistors are an important element of the power IC in the processing of high voltages.
Since the DMOS device is operated at high voltage, a device isolation layer having a high breakdown voltage is required between adjacent DMOS devices or between the DMOS device and other control circuits. Conventionally, junction isolation technology using an impurity-diffused layer for device isolation was employed for this purpose. However, in the case of junction isolation technology, the junction isolation structure requires a wide surface area in order to form deep device isolation structures, as the structure of the DMOS device requires thick epitaxial layers. In order to overcome this limitation, there has been introduced a method of forming a trench device isolation structure. U.S. Pat. No. 5,356,822, entitled “Method for making all complementary BICDMOS devices” introduces a method of isolating devices by forming a DMOS device on a silicon on insulator (SOI) substrate.
FIG. 1 is a sectional view of a conventional DMOS device having a device isolation structure employing the junction isolation technology.
Referring to FIG. 1, a DMOS device of the junction isolation structure includes a semiconductor substrate 1, a first conductivity type buried layer 6 placed on a predetermined region of the semiconductor substrate 1, and a second conductivity type buried layer 2 slightly spaced apart from the first conductivity type buried layer 6 and surrounding the buried layer 6. A first conductivity type epitaxial layer 8 is deposited on the entire surface of the first conductivity type layer 6, the second conductivity type layer 2, and the semiconductor substrate 1. The epitaxial layer 8 is more lightly doped than the first conductivity type buried layer 6. A second conductivity type junction isolation layer 4 is connected to the second conductivity type buried layer 2 while surrounding a predetermined region of the epitaxial layer 8. The junction isolation layer 4 and the second conductivity type buried layer 2 form a device isolation structure 5 of the DMOS device. The device isolation structure 5 defines the device region of the DMOS device. A field oxide layer 16 is placed in a predetermined region of the device region surrounded by the device isolation structure 5 to define a first active area and a second active area. The field oxide layer 16 surrounds the first active area spaced apart from the device isolation structure 5. A gate electrode 14 is placed on the first active area with a gate insulating layer 22 interposed there between. A source region is formed in the first active area adjacent to the gate electrode 14, and a drain region is formed in the second active area. The source region 26 includes a first conductivity type diffused layer 18 formed on the surface of the first active area adjacent to the gate electrode 14, a second conductivity type diffused layer 20 spaced apart from the gate electrode 14 adjacent to the first conductivity type diffused layer 18, and a second conductivity type body region 26 surrounding the first conductivity type diffused layer 18 and the second conductivity type diffused layer 20. The drain region includes a sink region 10 vertically penetrating the epitaxial layer 8 and connected to the first conductivity type buried layer 6, and a heavy doped region 12 formed on the surface of the second active area on the sink region 10. A field oxide layer 15 is further formed on the junction isolation layer 4 for device isolation.
Normally, the breakdown voltage of the DMOS device is proportional to the thickness of the epitaxial layer 8. That is, the epitaxial layer 8 is typically formed to have a thickness of over 10 μm, in order to provide a high breakdown voltage in the DMOS device. Therefore, when forming the second conductivity type junction isolation layer 4 through the thick epitaxial layer 8, and considering the diffusion of the impurity to form the second conductivity type junction isolation layer 4, the junction isolation layer and the drain region should be positioned a suitable distance apart. As a result, the area size occupied by the device isolation structure in the DMOS device employing the junction isolation technology is over 25% of the entire device region.
FIG. 2 is a sectional view of a DMOS device having a trench device isolation structure that was introduced in order to overcome the above-mentioned limitations in the traditional junction isolation structures.
Referring to FIG. 2, as in the junction isolation structures described above, a DMOS device having a trench device isolation structure includes a first conductivity type buried layer 36 formed on a semiconductor substrate 31, an epitaxial layer 38 covering the buried layer 36 and the semiconductor substrate 31, a gate electrode 34 formed on the epitaxial layer 38, a source region and a drain region. The source region and the drain region have the same structure as the corresponding parts of the DMOS device having the junction isolation structure. That is, the source region includes a first conductivity type diffused layer 48, a second conductivity type diffused layer 30, and a second body region 44. The drain region includes a sink region 40 connected to the buried layer 36, and a heavy doped region 42 formed on the upper side of the sink region 40. A device isolation structure 32 is placed to penetrate a portion of the epitaxial layer 38 and the semiconductor substrate 31. The device isolation structure 32 defines the device region. A field oxide layer 46 is placed on a predetermined region of the device region surrounded by the device isolation structure 32 to thereby define the first active area and the second active area. The gate electrode 34 and the source region are placed on the first active area surrounded by the field oxide layer 46. The drain region is placed in the second active area between the field oxide layer 46 and the device isolation structure 32.
As described above, the device isolation structure 32 is more deeply formed than the first conductivity type buried layer, in order to isolate between neighboring DMOS devices and between the DMOS devices and other control circuits. That is, the device isolation structure 32 has a thickness over about 20 μm in the DMOS device having a working voltage of about 70 V. However, there is a limit in forming the deep trench device isolation structure in such a small area because of difficulties in the etching and burying processes.